1. Field of the Invention
This invention relates to an improved method and system for testing multiple intellectual property cores contained within an integrated circuit, each core including a standard IEEE-1149.1 compliant test access port (TAP). A core is a predefined subcircuit function, which can be incorporated into the design of an integrated circuit. Some example core functions include but are not limited to: digital signal processors, microcontrollers, microprocessors, and memories. The present invention achieves the above mentioned testing without having to change or modify the standard TAPs of each core. Using the present invention, the TAPs of each core are made selectable such that they can be connected to the integrated circuit pins to enable direct communication between the integrated circuit pins and selected core TAPs.
2. Brief Description of the Prior Art
The IEEE-1149.1 standard, known as JTAG, is a standardized test system developed for testing chips on a board. A trend in the semiconductor industry is for popular chip functions to evolve into intellectual property core circuit functions to allow them to be provided for reuse in the design of larger, more complex integrated circuits. As semiconductor chips evolve into intellectual property cores, the JTAG test system may remain as an integral part of the core. Thus cores will contain the JTAG test system, which facilitates the testing of the cores in chips similar to the way JTAG facilitates the testing of chips on boards.
The present invention assumes plural cores of an integrated circuit each contain a standard IEEE 1149.1 TAP interface comprising a test data input (TDI), test data output (TDO), test mode select (TMS), test clock (TCK), and a test reset (TRST). According to the present invention, as will be described in detail below, a TAP Linking Module is located between the 1149.1 interfaces of the core TAPs and a corresponding 1149.1 test pin interface of the integrated circuit. The TAP Linking Module provides selectivity between the integrated circuit""s 1149.1 test pin interface and one or more of the core TAP 1149.1 test interfaces. Core testing takes place by connecting a tester of standard type to the integrated circuit test pins, communicating information via the test pins to the TAP Linking Module to select one or more of the core TAPs to be connected the test pins, and thereafter applying test patterns to the one or more cores via the connection formed by the TAP Linking Module.
It is important to note that some cores use the TAP not only for testing but also for emulation, debug, code development, and system level fault diagnosis. Therefore the present invention not only provides for selective core testing, but also for selective core emulation, debug, code development, and fault diagnosis operations.
A prior art paper entitled xe2x80x9cAn IEEE 1149.1 Test Access Architecture For ICs With Embedded Coresxe2x80x9d by Whetsel was published in the 1997 International Test Conference proceedings, pages 69-78, and is incorporated herein by reference. This paper provides detail on the problems associated with accessing TAPs of cores embedded in integrated circuits. Further, the paper provides a solution to this problem by describing how the design of standard TAPs of cores may be modified to enable them to operate in co-operation with a TAP Linking Module, such that one or more of the modified core TAPs may be selectively accessed for test and emulation via the TAP Linking Module.
Whetsel U.S. Pat. Nos. 5,056,093 and 5,054,024 describe a system for switching between TAPs by use of a Device Select Module (DSM). This approach locates the DSM between the tester and plurality of TAPs to allow the 1149.1 instruction and data scans to pass through the DSM and the currently selected TAPs. 1149.1 instruction and data scans are used to enable the DSM to switch between the TAPs. In this approach the DSM is scanned during every 1149.1 instruction and data scan operation to the selected TAPs. The TAP linking module of the present invention is scanned during every 1149.1 instruction scan operation to the selected TAPs, but not during 1149.1 data scan operations to the selected TAPs. 1149.1 data scan operations to the TAP linking module occurs only when no TAPs are selected for scanning. Thus 1149.1 data scans to the TAP linking module occur separate from 1149.1 data scan to the TAPs. The difference therefore between the DSM and TAP linking module is that the DSM is scanned along with the selected TAPs during 1149.1 data scans, while 1149.1 data scans to the TAP linking module occur separate from 1149.1 data scans to the TAPs.
The TAP linking module of the present invention provides the benefits described for the TAP linking module in the Whetsel paper, but without having to modify the design of the standard TAP. The importance of not having to modify the standard TAP can be seen in pre-existing (legacy) core designs which are not modifiable. For example, non-modifiable legacy cores with TAPs may be provided by intellectual property core vendors. Since the cores are not modifiable, their TAPs cannot be modified for use with the TAP Lining Module described in the Whetsel paper. The present invention provides a method of achieving the same advantages stated in the Whetsel paper but without having to modify the TAP design.
As described in the Whetsel paper, existing core TAP access techniques either; (1) provide extra test interface pins (TDI, TDO, TMS, TCK, TRST) on the integrated circuit for each TAP, or (2) string all TAPs together serially via their TDI and TDO signals and in parallel via their TMS, TCK, and TRST signals and connect the TAP string to one set of test interface pins on the integrated circuit. When extra test pins are used, each TAP has its own test interface. However, this approach requires the integrated circuit to have more test pins and the tester to have more scan interface resources. When core TAPs are connected in a string, the speed at which the string of TAPs may be serially operated (i.e. scanned) is dependant upon each TAP""s maximum TCK frequency rate. For example, a string of three TAPs may exist where the first TAP can operate at a 40 Mhz maximum TCK rate, the second TAP can operate at a 10 Mhz maximum TCK rate, and the third TAP can operate at a 50 Mhz maximum TCK rate. When scanning the string of TAPs, the TCK frequency rate of the string cannot exceed the maximum TCK rate of the second TAP. Therefore scan operations through the TAP string is limited to 10 Mhz, even though the first and third TAPs can operate at 40 and 50 Mhz, respectively. Also, stringing TAPs together does not allow one TAP to be placed in an 1149.1 RunBist self-test mode while the other TAPs are being scanned.
The present invention, as described in detail below, provides a TAP Linking Module design which uses instruction augmentation to achieve a TAP selection system supporting selectable access of non-modifiable TAPs contained within legacy cores.
In accordance with the present invention, selection and testing of multiple TAP""ed cores within a large integrated circuit can be performed without adding test interface pins beyond those specified by the IEEE 1149.1 standard, and without modifying the TAP design of the cores. This is accomplished by a novel design of the Tap Linking Module, referred to hereafter as TLM, which eliminates the need to redesign core TAPs.
Briefly, the present invention enables an IEEE 1149.1 test pin interface on an integrated circuit to access any number of standard TAPs within an integrated circuit by providing a TLM that is operable to switch the TAPs to the test pins in response to 1149.1 scan operations. No design modifications are required on TAPs used with the present invention.
It is an object of the present invention to provide the following features.
(1) Provide a TLM architecture for integrated circuits which operates to enable and disable 1149.1 scan access to TAPs without having to modify the design of TAPs. Hence, the invention can be used on legacy cores having non-modifiable TAPs.
(2) Maintain independent development of scan test patterns specific to each embedded core such that the scan test patterns may be directly applied to the core independent of other cores within the integrated circuit. Hence, maintenance and application of core scan test patterns is simplified.
(3) Allow for maximizing the scan test frequency (i.e. TCK frequencies) to each core independent of other cores whose scan test frequency may be less than the scan test frequency of the core being tested. Hence, core test times are reduced.
(4) Ability to re-use, without modification, the test patterns of a core in different integrated circuit designs utilizing the core. Hence, the ease of scan test pattern re-use between integrated circuits utilizing the same core is realized.
(5) Allow for core test integration to become the simple concatenation of the different re-usable scan test patterns of the different cores serially connected to the TLM. Hence, the goal of simplifying multiple core test integration is achieved.
In accordance with the present invention, there is provided a TLM architecture that attains the above described criteria and can accommodate access to multiple TAPs without having to modify the TAP designs. The invention is also compatible with the future looking definition of modifying TAPs as described in the Whetsel paper. The modified TAPs in the Whetsel paper require two extra signals in addition to the five test signals (TDI, TDO, TMS, TCK, TRST) defined in IEEE-1149.1, namely an enable and select signal. The Whetsel paper also requires one or more specific instructions to be added to the TAPs for enabling the switching between multiple TAPs.
The standard TAP as defined in IEEE 1149.1 has two scan operation modes; (1) a data scan operation mode whereby test data is serially communicated through the TAP via the TDI and TDO TAP signals, and (2) an instruction scan operation mode whereby instruction data is serially communicated through the TAP via the TDI and TDO TAP signals.
The present invention exploits the instruction scan operation mode of the TAP to enable the TLM to be loaded with instruction bits which are used to determine which core TAP will be connected to or disconnected from the integrated circuit test pins. During instruction scan operations, instruction data is scanned through both the connected TAP and an augmentation instruction shift register (AISR) within the TLM. The TLM""s AISR extend the instruction register length of the connected TAP by the number of the bits within the AISR. Thus during instruction scans, the present invention provides an over-shifting technique which allows instruction data to be loaded in both the instruction register of the connected TAP and the AISR of the TLM. The alignment of the TAP instruction register and the TLM AISR is by design choice. For example, the movement of the instruction data may first proceed through the TAP""s instruction register then through the AISR, or the movement of the instruction data may first proceed through the AISR then through the TAP""s instruction register.
It is important to note that the TLM""s AISR bits are only present in the scan path during TAP instruction scan operations, and not during TAP data scan operations. Thus, modifications of existing test description languages (TDL) that contain both TAP instruction and data scan frames need only modify the instruction scan frames of the TDL to use the present invention. Also, the instruction scan frame modifications only require extending the length of the TDL instruction frames to include the bit positions of the AISR. In each TDL instruction scan frame, the augmentation bits will be set to either; (1) establish a new TAP connection, or (2) maintain the existing TAP connection. Since the TDL data scan frames are not required to be modified by the present invention, core scan test pattern reuse is easily achieved by the present invention.
The concept of augmenting TAP instruction scan lengths to communicate data to a TLM is not limited for use within integrated circuits. For example, a TLM can be used at the board level to make various connection arrangements to TAPs of integrated circuits mounted boards. In this case, the TLM may exists as a separate integrated circuit on the board, or as a subcircuit of an integrated circuit on the board.
Briefly, the above process is accomplished by; (1) adding one or more bits to every TAP instruction scan pattern, (2) communicating the added bit or bits to the AISR of the TLM during instructions scan operations, (3) decoding the added bit or bits at the end of the instruction scan operations, and (4) depending upon the decoding, either maintaining the current TAP connection or forming a new TAP connection.